Method and apparatus for generating a clock signal and for controlling a clock frequency using the same

ABSTRACT

A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency. A masking pattern is created for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal. The clock signal, which includes the target frequency, is generated by discarding the number of pulses from the reference clock signal using the masking pattern.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

A claim of priority is made to Korean Patent Application No.10-2006-0088186, filed Sep. 12, 2006, the subject mater of which ishereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for generating aclock signal, and more particularly, to a method and apparatus forgenerating a clock signal from a reference clock signal.

2. Description of the Related Art

In general, clock signal generators are used in the field of electronicdevices, including semiconductors. More particularly, clock signalgenerators may be used in designing an electronic circuit, whichrequires a clock signal having a particular frequency to process data.If necessary, the clock signal generator executes frequency division ofreference clock signal to generate clock signals having a variety ofdifferent frequencies.

Korean Laid-open Patent No. 2000-0065911 discloses preventing glitchesproduced while generating clock signals, regardless of delay elements,and Japanese Laid-open Patent No. 2001-209454 discloses generating clocksignals, which are not integral numbers, using a circuit that generatesa polyphase clock.

According to the conventional art, a reference clock signal may bedivided by an integer to generate clock signals having a targetfrequency. For example, a reference clock signal having a frequency of100 MHz may be divided by integers to generate clock signals havingfrequencies of 50 MHz, 25 MHz, 12.5 MHz, and so on. However, when aclock signal having a target frequency of 75 MHz is required, a newreference clock signal is necessary. For example, a new reference clocksignal having a frequency of 300 MHz, which is the least common multipleof 100 MHz and 75 MHz, is required.

Accordingly, the conventional technology which divides a reference clocksignal by an integer to generate clock signals produces limitedfrequencies of clock signals, and therefore, in practice, a variety ofreference clock sources are needed

It may be possible to generate clock signals having a variety ofdifferent frequencies using a phase locked loop (PLL) circuit, but whena PLL circuit is used, a phase locking time can result in operationaldelays.

Moreover, clock signals having different frequencies generated from asource clock signal are not synchronized with one another. Thus, anadditional synchronizer is required for processing data, which decreasesprocessing speed.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a method of generating aclock signal, which includes determining a number of pulses to bediscarded from each predetermined cycle of a reference clock signal inorder to obtain, on average, a target frequency and creating a maskingpattern for discarding the number of pulses to be discarded from eachpredetermined cycle of the reference clock signal. The method furtherincludes generating the clock signal, having the target frequency, bydiscarding the number of pulses from the reference clock signal usingthe masking pattern. Determining the number of pulses to be discardedmay include obtaining a greatest common divisor (G.C.D.) of a frequencyof the reference clock signal and the target frequency; dividing each ofthe reference clock signal frequency and the target frequency by theG.C.D.; and determining a length of the predetermined cycle to includepulses of the reference clock signal. A number of the pulses is the sameas a value obtained by dividing the reference clock signal frequency bythe G.C.D. The number of pulses to be discarded is a difference betweenthe value obtained by dividing the reference clock signal frequency bythe G.C.D. and a value obtained by dividing the target frequency by theG.C.D. The masking pattern is used to change a location of at least oneclock pulse to be discarded from each predetermined cycle according toan initial set.

Another aspect of the present invention provides a method of generatinga target clock signal. The method includes calculating a pulse detectinglocation in a cycle, which includes a number of pulses corresponding toan inverse of a frequency of the target clock signal. A pulse of areference clock signal is detected, the detected pulse having apredetermined relationship with the calculated pulse detecting location.The target clock signal is generated using the detected pulse of thereference clock signal. The detected pulse of the reference clock signalmay be a closest pulse to the calculated pulse detecting location, apulse generated immediately before or after the calculated pulsedetecting location, or a pulse generated an initially set number ofpulses after the calculated pulse detecting location. Also, a duty ratioof the generated target clock signal may be changed to comply with aninitially set standard.

Another aspect of the present invention provides a method of generatinga target clock signal. The method includes receiving an externallyprovided clock signal for detecting a pulse, the clock signal having atarget frequency; detecting a pulse of a reference clock signal inrelation to a pulse occurrence location of the clock signal fordetecting a pulse; and generating the target clock signal using thedetected pulse of the reference clock signal.

Another aspect of the present invention provides a method of controllinga clock frequency. The method includes generating a clock signal for anapplication having, on average, a target frequency from a referenceclock signal, and calculating a data processing progress percentage ofprocessing data using the clock signal. A difference is determinedbetween the calculated data processing progress percentage and a targetprogress percentage. The target frequency of the clock signal is thenchanged based on the determined difference. Changing the targetfrequency of the clock signal may include decreasing the targetfrequency of the clock signal when the calculated progress percentage isgreater than the target progress percentage by a first predeterminedamount, and increasing the target frequency of the clock signal when thecalculated progress percentage is less than the target progresspercentage by a second predetermined amount.

Generating the clock signal for the application may include discarding acalculated number of pulses from each section of the reference clocksignal, so that the reference clock signal includes, on average, thetarget frequency. Also, generating the clock signal may includecalculating a pulse detecting location in multiple cycles of thereference clock signal, where the number of pulses of each cyclecorresponds to an inverse of the target frequency, and detecting a pulseof the reference clock signal closest to the calculated pulse detectinglocation.

Another aspect of the present invention provides a device for generatinga clock signal for an application, including a reference clockgenerator, a masking pattern generator and an AND gate. The referenceclock generator generates a reference clock signal having multiple clockpulses. The masking pattern generator creates a masking pattern todiscard at least one clock pulse of the clock pulses from the referenceclock signal in order to generate a target frequency from the referenceclock signal. The AND gate generates the clock signal for theapplication by logically multiplying the reference clock signal and themasking pattern. The masking pattern generator may include a counter forcounting a number of pulses of the reference clock signal, and a mappingunit for outputting signals having logic values mapped to either 0 or 1,based on a ratio of the frequency of the reference clock signal to thetarget frequency. The counter may count in units of N, where N is avalue obtained by dividing the frequency of the reference clock signalby a greatest common divisor (G.C.D.) of the frequency of the referenceclock signal and the target frequency.

Another aspect of the present invention provides a device for generatinga clock signal for an application. The device includes a reference clockgenerator, a microprocessor and a pulse detector. The reference clockgenerator generates a reference clock signal. The microprocessorcalculates a pulse detecting location in multiple cycles, each cycleincluding a number of pulses corresponding to an inverse of a targetfrequency of a clock signal for an application. The pulse detectorgenerates the clock signal by detecting a pulse of the reference clocksignal having a predetermined relationship with the pulse detectinglocation. For example, the pulse detector may detect the pulse of thereference clock signal closest to the calculated pulse detectinglocation, the pulse generated immediately before or after the calculatedpulse detecting location, or the pulse generated an initially set numberof pulses after the calculated pulse detecting location. The device mayalso include a duty alteration circuit configured to change a duty ofthe clock signal output from the pulse detector to comply with aninitially set standard.

Yet another aspect of the present invention provides a device forcontrolling a clock frequency, including a clock signal generatingcircuit, an application circuit and a microprocessor. The clock signalgenerating circuit is configured to generate a clock signal for anapplication, where the clock signal has a target frequency from areference clock signal. The application circuit is configured to processdata using the clock signal for the application. The microprocessor isconfigured to calculate a data processing progress percentage of theapplication circuit and to control the clock signal generating circuitto change the target frequency based on a difference between thecalculated data processing progress percentage and a target progresspercentage. The microprocessor may be further configured to control theclock signal generating circuit to decrease a frequency of the clocksignal when the calculated progress percentage is greater than thetarget progress percentage by a first predetermined amount, and toincrease the frequency of the clock signal when the calculated progresspercentage is less than the target progress percentage by a secondpredetermined amount.

The clock signal generating circuit may include a masking patterngenerator for creating a masking pattern to discard at least one pulsefrom the reference clock signal to obtain the target frequency from thereference clock signal, and an AND gate for generating the clock signalfor the application by logically multiplying the reference clock signaland the masking pattern. Also, the clock signal generating circuit mayinclude an arithmetic circuit for calculating a pulse detecting locationin multiple cycles, each cycle having a number of pulses correspondingto an inverse of the target frequency of the clock signal for theapplication, and a pulse detector for detecting a pulse of the referenceclock signal generated closest to the pulse detecting location.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the present invention will be described withreference to the attached drawings, in which:

FIG. 1 is a configuration diagram of a masking pattern generating devicefor generating a clock signal, according to an embodiment of the presentinvention;

FIG. 2 is a circuitry structure of the masking pattern generatorillustrated in FIG. 1, according to an embodiment of the presentinvention;

FIG. 3 is an example of a mapping table adapted to an embodiment of thepresent invention;

FIG. 4 is a configuration diagram of a device for generating a clocksignal, according to an embodiment of the present invention;

FIG. 5 is a configuration diagram of a device for controlling a clockfrequency, according to an embodiment of the present invention;

FIG. 6 is a flowchart depicting a method of generating a clock signal,according to an embodiment of the present invention;

FIG. 7 is a flowchart depicting a method of generating a clock signalaccording to another embodiment of the present invention;

FIG. 8 is a flowchart depicting a method of generating a clock signalaccording to another embodiment of the present invention;

FIG. 9 is a flowchart depicting a method of controlling a clock signal,according to an embodiment of the present invention;

FIG. 10 is a timing diagram of significant signals used for the device,according to an embodiment of the present invention;

FIG. 11 is a timing diagram of significant signals used for the device,according to another embodiment of the present invention; and

FIG. 12 is a timing diagram of significant signals used for the device,according to another embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The accompanying drawings are referred to in order to facilitatedescriptions of various embodiments of the present invention, the meritsthereof, and the objectives accomplished by the implementation of thepresent invention.

Hereinafter, the present invention will be described in detail byexplaining various embodiments with reference to the attached drawings.Like reference numerals in the drawings denote like elements.

The present invention includes the following two methods to generate aclock signal.

A first method is to generate a target clock signal having a targetfrequency by discarding some clock pulses of a reference clock signal.In other words, some of the clock pulses are removed to adjust afrequency to the target frequency. In this manner, pulse intervals arenot uniform, although average frequencies may generally be adjusted tothe target frequency. For example, a reference clock signal of 100 MHzmay be adjusted to a target clock signal of 70 MHz. The pulses of thereference clock signal are divided into groups of ten, and three pulsesare deleted from each group of ten. The target clock signal of 70 MHzmay then be obtained.

A second method is to generate a target clock signal by calculating apulse detecting position corresponding to a target frequency, anddetecting a clock pulse of a reference clock signal having apredetermined relationship, e.g., the closest pulse, with the calculatedposition.

Accordingly, in both methods, edge positions of the target clock signalsare the same as edge positions of the reference clock signals.

Exemplary embodiments of the clock signal generating methods accordingto the present invention will be described below.

With respect to the first method, FIG. 1 is a configuration diagram of adevice for generating a clock signal according to an embodiment of thepresent invention. Referring to FIG. 1, the device includes a referenceclock generator 110, a masking pattern generator 120, and an AND gate130.

The reference clock generator 110 generates a reference clock signal,which is a source clock signal used by an electronic device. Thereference clock signal may be generated using, for example, anoscillating element, such as a crystal or ceramic oscillator. Theelectronic device derives desired or target clock signals, required byvarious applications, using the reference clock signal. Therefore, thefrequency of the reference clock signal is set higher than the frequencyof the derived clock signals.

The masking pattern generator 120 creates a master pattern fordiscarding some clock pulses of the reference clock signal in order togenerate a target frequency from the reference clock signal. FIG. 2illustrates an exemplary circuit structure of the masking patterngenerator 120, in detail.

Referring to FIG. 2, the masking pattern generator 120 includes acounter 120-1, a memory 120-2 for storing a mapping table, and a mappingunit 120-3. The counter 120-1 counts in units of N (where N is aninteger). N may be determined based on the frequency of the referenceclock signal and a target frequency of a desired clock signal. In otherwords, N may be determined by dividing the frequency of the referenceclock signal by the greatest common divisor (G.C.D.) of the frequency ofthe reference clock signal and the target frequency.

For example, when the frequency of the reference clock signal is 100 MHzand the target frequency of a clock signal to be derived is 70 MHz, theG.C.D. of the frequencies is 10,000,000. As such, a value obtained bydividing the frequency of the reference clock signal by the G.C.D. is10. Thus, in this case, the counter 120-1 is set to a decimal counter.

The memory 120-2 stores a mapping table which maps output values of thecounter 120-1 to 0 or 1. A mapping method according to the presentembodiment is to map 1 and 0 according to the proportion of a frequencyof the reference clock signal to a target frequency of a derived clocksignal.

For instance, when a frequency of the reference clock signal is 100 MHzand a target frequency of the derived clock signal is 70 MHz, the ratioof the numbers of 1 to 0 in the mapping table is 7:3. Specifically, inthe mapping table, seven out of ten values from 0 to 9 of the decimalcounter are mapped to 1, and the other three values are mapped to 0.FIG. 3 shows an example of the mapping table depicting this case. InFIG. 3, the counter values 0, 8, and 9 are mapped to 0, and theremaining counter values are mapped to 1.

According to the present embodiment, the number of the counter valueswhich will be mapped to 0 or 1 is significant for the mapping table.However, the specific counter output values which will be mapped to 0 or1 can be variously set. For example, the average frequency of the clocksignal generated when the counter values of 0, 8, and 9 are mapped to 0and the remaining counter values are mapped to 1 is the same as theaverage frequency of the clock signal generated when the counter valuesof 1, 3, and 5 are mapped to 0 and the remaining counter values aremapped to 1.

The mapping unit 120-3 of FIG. 2 uses the mapping table stored in thememory 120-2 to create a masking pattern corresponding to a logic valueof 0 or 1, which is mapped to values output from the counter 120-1.

Referring again to FIG. 1, the reference clock signal (a) generated bythe reference clock generator 110 and the masking pattern (b) created bythe masking pattern generator 120 are input to the AND gate 130. The ANDgate 130 then outputs a signal corresponding to an output of an ANDoperation of the reference clock signal (a) and the masking pattern (b).For example, the AND gate 130 logically multiplies the reference clocksignal (a) and the masking pattern (b). The signal output from the ANDgate 130 becomes the target clock signal (c), which has a frequencydesired to be generated from the reference clock signal.

Referring to the example shown in FIG. 10, when a frequency of areference clock signal (a) is 100 MHz and a target frequency of a targetclock signal (c) to be derived from the reference clock signal (a) is 70MHz, a masking pattern (b) is generated using the mapping tableillustrated in FIG. 3. Thus, the target clock signal (c) has an averagefrequency of 70 MHz.

According to the present embodiment, pulse intervals of the target clocksignal (c) are not uniform. Rather, when pulses of the reference clocksignal (a) are divided into groups of ten, for example, and three pulsesof each group of ten are deleted, the target average frequency of 70 MHzcan be obtained. Further, a pulse edge of the target clock signal (c) isexactly matched to a pulse edge of the reference clock signal (a), andthus an additional synchronizer is not necessary.

FIG. 6 is a flowchart illustrating a method of generating a clock signalaccording to an embodiment of the present invention. Referring to FIG.6, the number of pulses to be deleted from pulses of a reference clocksignal in each cycle is determined based on a frequency of a targetclock signal, which is to be derived from the reference clock signalthat is a source clock signal (S610).

To determine the cycles and the number of the clock pulses deleted fromthe reference clock signal for each cycle, the greatest common devisor(G.C.D.) of the frequency of the reference clock signal and thefrequency of the target clock signal is calculated. Then, thefrequencies of the reference clock signal and of the target clock signalare each divided by the G.C.D. A length of each cycle is determined bysection length, which includes reference clock pulses having the samenumber as the value obtained by dividing the reference clock signal bythe G.C.D. Then, the number of pulses to be deleted from every cycle isdetermined by subtracting the value obtained by dividing the frequencyof the target clock signal by the G.C.D. from the value obtained bydividing the frequency of the reference clock signal by the G.C.D.

For example, when the frequency of the reference clock signal is 100 MHzand the target frequency of the target clock signal to be derived is 70MHz, the G.C.D. is 10,000,000 (i.e., the largest integer by which bothfrequencies may be divided, with no remainder). Then, the value ofdividing the frequency of the reference clock signal by the G.C.D. is10, and the value of dividing the frequency of the target clock signalby the G.C.D. is 7. Therefore, in this case, the length of thepredetermined cycle is to include 10 reference clock pulses, and thenumber of pulses to be removed from each of the cycles is 3.

Next, a masking pattern is created based on the cycles and the number ofthe reference clock signals determined in operation S610 (S620). Forexample, it is assumed that the predetermined cycle has the length whichincludes 10 clock pluses and the number of clock pulses to be removedfrom the cycle is 3. The masking pattern is created to maintain threepulses out of the ten reference clock pulses at a low level, and tomaintain the remaining seven pulses at a high level, as illustrated inFIG. 10.

Then, the masking pattern created in operation S620 is adapted togenerate a target clock signal by discarding some clock pulses of thereference clock signal (S630). For example, in accordance with themasking pattern illustrated in FIG. 10, the reference clock pulsesincluded in sections of the masking pattern which maintain the pluses ata low level are removed, and the reference clock pulses included insections of the masking pattern which maintain the pulses at a highlevel are output intact. Accordingly, the clock pulse intervals of thetarget clock signal are not uniform, but the average frequency matchesthat of the target clock signal

If the masking pattern is designed to change which pulses will beremoved from a predetermined cycle according to initially set rules,electromagnetic wave energy can be dispersed over various frequencybands, and thereby improving electromagnetic interference (EMI).

With respect to the second method, FIG. 4 is a block diagram of a devicefor generating a clock signal according to another embodiment of thepresent invention. Referring to FIG. 4, the device includes a referenceclock generator 410, a microprocessor 420, a pulse detector 430, and aduty alteration circuit 440.

The reference clock generator 410 generates a reference clock signalwhich is a source clock signal used by an electronic system using, forexample, an oscillating element, such as a crystal or ceramicoscillator. The system derives desired clock signals required forvarious applications using the reference clock signal. Therefore, afrequency of the reference clock signal is designed to be higher than afrequency of a target clock signal.

The microprocessor 420 calculates a pulse detecting position in cycles,each cycle having a number of pulses corresponding to the inverse of atarget frequency of a clock signal for an application. In other words, acycle starting position of the clock signal for an application issubsequently calculated based on the reference clock signal. Here, thecycle starting position of the clock signal for an applicationcorresponds to the pulse detecting position. FIG. 11 shows a clocksignal for detecting pulses, which is the clock signal that has clockcycles of which a starting position is the calculated pulse detectingposition. However, when a target frequency of the clock signal for anapplication is not a divisor of the frequency of the reference clocksignal, the result is a fraction or decimal. If the calculated pulsedetecting position is a value having digits below the decimal point, itmeans that the pulse detecting position is not the same as a pulse edgeposition of the reference clock signal.

The pulse detector 430 generates the clock signal for an application bydetecting the pulse of the reference clock signal which has a specifiedor predetermined relationship with the calculated pulse detectingposition, for example, the pulse produced closest to the calculatedpulse detecting position. The pulse detector 430 can detect a referenceclock at a point where the pulse detecting position matches a pulse edgeof the reference clock signal, but otherwise should detect a pulse ofthe reference clock signal which has a specified relationship to thepulse detecting position.

The specified relationship may be determined according to particularrules, examples of which are as follows. First, the detected pulse ofthe reference clock signal may be a pulse that is generated closest tothe calculated pulse detecting position. In this case, the pulse of thereference clock signal is detected by rounding off decimals. Second, thedetected pulse of the reference clock signal may be a pulse that isgenerated immediately before the calculated pulse detecting position.When the pulse of the reference clock signal is detected in this way, anearly detecting clock signal for an application is obtained, asillustrated, for example, in FIG. 11. Third, the detected pulse of thereference clock signal may be a pulse that is generated immediatelyafter the calculated pulse detecting position. According to this rule, alate detecting clock signal for an application is obtained, asillustrated, for example, in FIG. 11. Fourth, the detected pulse of thereference clock signal may be a pulse that is generated afterpredetermined number of cycles from the calculated pulse detectingposition.

Applying these exemplary rules, a pulse edge of the clock signal for anapplication which is output from the pulse detector 430 exactly matchesa pulse edge of the reference clock signal, and its pulse intervals areuniform. However, as illustrated in FIG. 11, a duty ratio of the targetclock signal is reduced. To compensate for the reduction of the dutyratio, the duty ratio alteration circuit 440 of FIG. 4 increases theduty ratio, as illustrated in FIG. 12. For example, in the target clocksignal, when the length of a span of pulses at a logic “high” level isincreased to the length of two cycles of the reference clock signal, theduty of the target clock signal increases, as illustrated in FIG. 12.

In an embodiment, the duty alteration circuit 440 is optional. The dutyalteration circuit 440 may thus be omitted when an application whichprocesses data using the target clock signal can operate stably with atarget clock signal having a low duty ratio.

FIG. 7 is a flowchart illustrating a method of generating a clock signalaccording to another embodiment of the present invention. Referring toFIG. 7, a pulse detecting position of a reference clock signal isdetected in cycles, each cycle having a number of pulses correspondingto the inverse of a target frequency of a reference clock signal (S710).In other words, a cycle starting position is constantly detected basedon the reference clock signal. Here, the cycle starting positioncorresponds to the pulse detecting position.

Next, a pulse of the reference clock signal which is generated relativeto the calculated pulse detecting position is detected (S720). Asdiscussed above, there are several methods to detect the pulse of thereference clock signal, such as, detecting the pulse generated closestto the calculated pulse detecting position, detecting the pulsegenerated immediately before the calculated pulse detecting position,detecting the pulse generated immediately after the calculated pulsedetecting position, or detecting the pulse generated after apredetermined number of cycles from the calculated pulse detectingposition.

The target clock signal is generated using the pulse of the referenceclock signal which has been detected in operation S720 (S730).Accordingly, the target clock signal is produced by discarding somepulses of the reference clock signal.

Then, a duty ratio of the target clock signal produced in operation S730may be adjusted (S740). For example, the duty ratio can be increased byextending the length of a span of pulses at a logic “high” level in thetarget clock signal to the length of the reference clock signal's cycle,which has been initially set. In an embodiment, operation S740 isoptional. For example, it may be omitted when an application whichprocesses data using the target clock signal can operate stably with atarget clock signal having a low duty ratio.

FIG. 8 is a flowchart illustrating a method of generating a clock signalaccording to another embodiment of the present invention. To generate atarget clock signal, the method illustrated in FIG. 7 involvescalculating the pulse detecting position of the reference clock signal.In comparison, the method illustrated in FIG. 8 involves receiving aclock signal for detecting an externally provided pulse, the clocksignal corresponding to a frequency of a target clock signal.

Initially, an externally provided clock signal is received (S810). Thereceived clock signal has a frequency which is the same as a targetfrequency intended to be generated.

Then, a pulse of a reference clock signal is detected using the receivedclock signal as the clock signal for detecting the pulse (S820). Thereare several methods to detect the pulse of the reference clock signalusing the externally provided clock signal, such as, to detect the pulseclosest to a rising edge of the clock signal for detecting the pulse, todetect the pulse generated immediately before the rising edge of theclock signal for detecting the pulse, to detect the pulse generatedimmediately after the rising edge of the clock signal for detecting thepulse, or to detect the pulse generated a predetermined number of cyclesfrom the rising edge of the clock signal for detecting the pulse. In anexemplary embodiment, the pulse of the reference clock signal isdetected in relation to the occurrence of the rising edge of the clocksignal for detecting the pulse. Alternatively, the pulse of thereference clock signal may be detected at the occurrence of the fallingedge of the clock signal for detecting the pulse.

The final target clock signal is generated using the detected pulse ofthe reference clock signal (S830). That is, the final target clocksignal is generated by discarding some of the pulses of the referenceclock signal.

Then, a duty ratio of the target clock signal generated in operationS830 is adjusted (S840). For instance, the duty ratio of the targetclock signal may be increased by extending the length of a span ofpulses at a logic “high” level in the target clock signal to thereference clock signal's initially set cycle length. In an embodiment,operation S840 is optional, and it can be omitted when an applicationwhich processes data using the target clock signal can operate stablywith a target clock signal having a low duty ratio.

Accordingly, when the frequency of the target clock signal cannot begenerated from the reference clock signal by using a frequency divider,an edge position of a target clock signal externally generated does notmatch the edge position of the reference clock signal. However, the edgeposition of the target clock signal generated according to the presentmethod corresponds to the edge position of the reference clock signal,and the target clock signal has uniform clock intervals.

FIG. 5 is a block diagram depicting a device for controlling a clockfrequency according to an embodiment of the present invention. Referringto FIG. 5, the device includes a clock signal generating circuit 510, amicroprocessor 520, and a plurality of applications AP(1), AP(2), . . ., AP(n).

The clock signal generating circuit 510 generates clock signals havingtarget frequencies corresponding to each of the applications AP(1),AP(2), . . . , AP(n). In an embodiment, the circuitry structure of theclock signal generating circuit 510 is similar to the structure of thereference clock generator 110, described with respect to FIG. 1, or thereference clock generator 410, described with respect to FIG. 4.

Each of the applications AP(1), AP(2), . . . , AP(n) processes data inresponse to commands from the microprocessor 520. The applicationsAP(1), AP(2), . . . , AP(n) may include, for example, a video/audiosignal processing application, a data storing and reading application, adata communication processing application, and the like.

The microprocessor 520 controls applications AP(1), AP(2), . . . ,AP(n). For example, when issuing commands instructing each of theapplications to process a certain operation, the microprocessor 520 maycalculate the percentage of progress, which is how much an applicationhas processed its respective operation. The microprocessor 520 may thencontrol the clock signal generating circuit 510 to change a clockfrequency of a corresponding application based on the difference betweenthe calculated progress percentage and a target progress percentageassociated with the operation being processed by the application.Methods of calculating progress percentages of an operation arewell-known, and thus are not specifically described herein.

The microprocessor 520 controls the clock signal generating circuit 510to decrease the frequency of a clock used by an application when thecalculated progress percentage of processing the operation is greaterthan the target progress percentage, for example, by a predeterminedamount. Alternatively, the microprocessor 520 controls the clock signalgenerating circuit 510 to increase the frequency of the clock when thecalculated progress percentage of processing the operation is less thanthe target progress percentage, for example, by a predetermined amount,which may be the same as the predetermined amount used to determine whento decrease the clock frequency.

As stated above, the circuitry structure of the clock signal generatingcircuit 510 may be similar to that of the reference clock generators 110or 410, described with respect to FIG. 1 or FIG. 4, respectively. Whenthe clock signal generating circuit 510 is similar to the referenceclock generator 110 illustrated in FIG. 1, the clock frequency may beadjusted by changing a mapping table of the masking pattern generator120. When the clock signal generating circuit 510 is similar to thereference clock generator 410 illustrated in FIG. 4, the clock frequencymay be adjusted by changing a pulse detecting position of the referenceclock signal.

FIG. 9 is a flowchart illustrating a method of controlling a clockfrequency, according to an embodiment of the present invention. A clocksignal for an application is generated to have an initially setfrequency (S910). The clock signal may be generated by discarding somepulses of a reference clock signal acting as the source clock signal.Alternatively, the clock signal may be generated by calculating a pulsedetecting position from the reference clock signal which corresponds tothe target frequency, and detecting a clock pulse of the reference clocksignal having a predetermined relationship with the calculated position,e.g., the clock pulse closest to the calculated position, as discussedabove.

A progress percentage is calculated, indicating how much the applicationhas processed data in accordance with a corresponding operation (S920).The progress percentage may be obtained, for example, as a ratio of anamount of an operation which has been currently processed to a totalamount of the operation to be processed.

The calculated progress percentage is compared to a target progresspercentage (S930). The target progress percentage may be obtained, forexample, as a ratio of the target amount of an operation which shouldhave been processed at that point in time to the total amount of theoperation to be processed.

The frequency of the clock used by the application may be changed bycomparing the results of the calculated progress percentage and thetarget progress percentage (S940). More particularly, the frequency ofthe clock used by the corresponding application is decreased when thecalculated progress percentage is greater than the target progresspercentage, for example, by a predetermined threshold for exceeding thetarget progress percentage. Likewise, the frequency of the clock isincreased when the calculated progress percentage is less than thetarget progress percentage, for example, by a predetermined thresholdfor not exceeding the target progress percentage. Accordingly, the clockfrequency used by the application may be adaptively adjusted,considering the corresponding progress percentage of processing thedata.

As described above, according to various embodiments of the presentinvention, some clock pulses of a reference clock signal may bediscarded or detected to generate a clock signal (generally having atarget frequency) from the reference clock signal. Accordingly, thefollowing exemplary results of may be obtained: First, a clock signalhaving a desired frequency can be generated using a simple circuit.Second, clock signals having frequencies that cannot be generated usinga frequency divider can be produced without adding new reference clocksignals. Third, an edge position of a derived clock signal is controlledto correspond to an edge position of a reference clock signal, thuseliminating the need for an additional synchronizer. Fourth, an averagefrequency of a created clock signal matches an average frequency of atarget frequency, and the frequency of the created clock signal can bevaried locally, thus reducing the effects of EMI. Fifth, a frequency ofa target clock signal can be adjusted by changing the number of pulsesdiscarded from a reference clock signal or by changing a clock signaldetecting position. Sixth, a frequency of a clock signal used by anapplication can be adaptively adjusted for optimization, considering anoperation processing progress percentage of the application.

Various embodiments of the present invention may include a method, adevice, a system and software. When embodied as software, aspects of thepresent invention are necessarily code segments for performing requiredoperations. A computer program including the code segments may be storedin a processor readable medium and transmitted through computer datasignals combined with carrier waves over a transmission medium and/or acommunication network. The processor readable medium includes any mediumthat can store or transmit data. Examples of processor readable mediainclude an electronic circuit, a semiconductor memory device, a ROM, aFlash memory, an erasable ROM (EROM), a floppy disk, an optical disk, ahard disk, an optical fiber medium, a radio frequency (RF) network, etc.Computer data signals include any signals which can be transmittedthrough a transmission medium, such as an electronic network channel,optical fiber, air, an electromagnetic field, an RF network, etc.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it is not limitedthereto. It will be apparent to those of ordinary skill in the art thatvarious changes in form and details may be made therein withoutdeparting from the spirit and scope of the present invention.

1. A method of generating a clock signal, the method comprising:determining a number of pulses to be discarded from each predeterminedcycle of a reference clock signal in order to obtain, on average, atarget frequency; creating a masking pattern for discarding the numberof pulses to be discarded from each predetermined cycle of the referenceclock signal; and generating the clock signal, comprising the targetfrequency, by discarding the number of pulses from the reference clocksignal using the masking pattern.
 2. The method of claim 1, whereindetermining the number of pulses to be discarded comprises: obtaining agreatest common divisor (G.C.D.) of a frequency of the reference clocksignal and the target frequency; dividing each of the reference clocksignal frequency and the target frequency by the G.C.D.; and determininga length of the predetermined cycle to include pulses of the referenceclock signal, a number of the pulses being equal a value obtained bydividing the reference clock signal frequency by the G.C.D.; the numberof pulses to be discarded comprising a difference between the valueobtained by dividing the reference clock signal frequency by the G.C.D.and a value obtained by dividing the target frequency by the G.C.D. 3.The method of claim 1, further comprising: changing a location of atleast one clock pulse to be discarded from each predetermined cycle,according to an initial set, using the masking pattern.
 4. A method ofgenerating a target clock signal, the method comprising: calculating apulse detecting location in a cycle, the cycle comprising a number ofpulses corresponding to an inverse of a frequency of the target clocksignal; detecting a pulse of a reference clock signal, the detectedpulse having a predetermined relationship with the calculated pulsedetecting location; and generating the target clock signal using thedetected pulse of the reference clock signal.
 5. The method of claim 4,wherein the detected pulse of the reference clock signal comprises aclosest pulse to the calculated pulse detecting location.
 6. The methodof claim 4, wherein the detected pulse of the reference clock signalcomprises a pulse generated immediately before the calculated pulsedetecting location.
 7. The method of claim 4, wherein the detected pulseof the reference clock signal comprises a pulse generated immediatelyafter the calculated pulse detecting location.
 8. The method of claim 4,wherein the detected pulse of the reference clock signal comprises apulse generated an initially set number of pulses after the calculatedpulse detecting location.
 9. The method of claim 4, further comprising:changing a duty ratio of the generated target clock signal to complywith an initially set standard.
 10. A method of generating a targetclock signal, the method comprising: receiving an externally providedclock signal for detecting a pulse, the clock signal having a targetfrequency; detecting a pulse of a reference clock signal in relation toa pulse occurrence location of the clock signal for detecting a pulse;and generating the target clock signal using the detected pulse of thereference clock signal.
 11. The method of claim 10, wherein the detectedpulse of the reference clock signal comprises a pulse generatedimmediately after the calculated pulse detecting location.
 12. Themethod of claim 10, wherein the detected pulse of the reference clocksignal comprises a pulse generated an initially set number of pulsesafter the calculated pulse detecting location.
 13. The method of claim10, further comprising: changing a duty of the generated target clocksignal to comply with an initially set standard.
 14. A method ofcontrolling a clock frequency, the method comprising: generating a clocksignal for an application having, on average, a target frequency from areference clock signal; calculating a data processing progresspercentage of processing data using the clock signal; determining adifference between the calculated data processing progress percentageand a target progress percentage; and changing the target frequency ofthe clock signal based on the determined difference.
 15. The method ofclaim 14, wherein generating the clock signal for the applicationcomprises discarding a calculated number of pulses from each of aplurality of sections of the reference clock signal, so that thereference clock signal comprises, on average, the target frequency. 16.The method of claim 14, wherein generating the clock signal for theapplication comprises: calculating a pulse detecting location in aplurality of cycles of the reference clock signal, a number of pulses ofa cycle corresponding to an inverse of the target frequency; anddetecting a pulse of the reference clock signal closest to thecalculated pulse detecting location.
 17. The method of claim 14, whereinchanging the target frequency of the clock signal comprises: decreasingthe target frequency of the clock signal when the calculated progresspercentage is greater than the target progress percentage by a firstpredetermined amount; and increasing the target frequency of the clocksignal when the calculated progress percentage is less than the targetprogress percentage by a second predetermined amount.
 18. A device forgenerating a clock signal for an application, the device comprising: areference clock generator configured to generate a reference clocksignal comprising a plurality of clock pulses; a masking patterngenerator configured to create a masking pattern to discard at least oneclock pulse of the plurality of clock pulses from the reference clocksignal to generate a target frequency from the reference clock signal;and an AND gate configured to generate the clock signal for theapplication by logically multiplying the reference clock signal and themasking pattern.
 19. The device of claim 18, wherein the masking patterngenerator comprises: a counter configured to count a number of pulses ofthe reference clock signal; and a mapping unit configured to outputsignals having logic values mapped to either 0 or 1, based on a ratio ofthe frequency of the reference clock signal to the target frequency. 20.The device of claim 19, wherein the counter is further configured tocount in units of N, where N comprises a value obtained by dividing thefrequency of the reference clock signal by a greatest common devisor(G.C.D.) of the frequency of the reference clock signal and the targetfrequency
 21. A device for generating a clock signal for an application,the device comprising: a reference clock generator configured togenerate a reference clock signal; a microprocessor configured tocalculate a pulse detecting location in a plurality of cycles, eachcycle comprising a number of pulses corresponding to an inverse of atarget frequency of a clock signal for an application; and a pulsedetector configured to generate the clock signal by detecting a pulse ofthe reference clock signal having a predetermined relationship with thepulse detecting location.
 22. The device of claim 21, wherein the pulsedetector detects the pulse of the reference clock signal closest to thecalculated pulse detecting location.
 23. The device of claim 21, whereinthe pulse detector detects the pulse of the reference clock signalgenerated immediately before the calculated pulse detecting location.24. The device of claim 21, wherein the pulse detector detects the pulseof the reference clock signal generated immediately after the calculatedpulse detecting location.
 25. The device of claim 21, wherein the pulsedetector detects the pulse of the reference clock signal generated aninitially set number of pulses after the calculated pulse detectinglocation.
 26. The device of claim 21, further comprising: a dutyalteration circuit configured to change a duty of the clock signaloutput from the pulse detector to comply with an initially set standard.27. A device for controlling a clock frequency, the device comprising: aclock signal generating circuit configured to generate a clock signalfor an application, the clock signal having a target frequency from areference clock signal; an application circuit configured to processdata using the clock signal for the application; and a microprocessorconfigured to calculate a data processing progress percentage of theapplication circuit and to control the clock signal generating circuitto change the target frequency based on a difference between thecalculated data processing progress percentage and a target progresspercentage.
 28. The device of claim 27, wherein the clock signalgenerating circuit comprises: a masking pattern generator configured tocreate a masking pattern to discard at least one pulse from thereference clock signal to obtain the target frequency from the referenceclock signal; and an AND gate configured to generate the clock signalfor the application by logically multiplying the reference clock signaland the masking pattern.
 29. The device of claim 27, wherein the clocksignal generating circuit comprises: an arithmetic circuit configured tocalculate a pulse detecting location in a plurality of cycles, eachcycle comprising a number of pulses corresponding to an inverse of thetarget frequency of the clock signal for the application; and a pulsedetector configured to detect a pulse of the reference clock signalgenerated closest to the pulse detecting location.
 30. The device ofclaim 27, wherein the microprocessor is further configured to controlthe clock signal generating circuit to decrease a frequency of the clocksignal when the calculated progress percentage is greater than thetarget progress percentage by a first predetermined amount, and toincrease the frequency of the clock signal when the calculated progresspercentage is less than the target progress percent by a secondpredetermined amount.